SN74LVC08DR

positive-AND gate, –0.5 V to 6.5 V, EPIC, SOIC14, ESD Protection, Texas Instruments

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PartNumber:: SN74LVC08DR

Brand:: Texas Instruments - TI | Pack: SOIC | D/C: 06+

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Products Upload time: 2011-11-28

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Product Summary

The SN74LVC08DR quadruple 2-input positive-AND gate is designed for 2.7-V to 3.6-V VCC operation. The SN74LVC08DR performs the Boolean function Y = A·B or Y=A+B in positive logic. Inputs can be driven from either 3.3-V or 5-V devices. This feature of SN74LVC08DR allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

Parametrics

SN74LVC08DR absolute maximum ratings: (1)Supply voltage range, VCC: –0.5 V to 6.5 V; (2)Input voltage range, VI: –0.5 V to 6.5 V; (3)Output voltage range, VO: –0.5 V to VCC + 0.5 V; (4)Input clamp current, IIK (VI < 0): –50 mA; (5)Output clamp current, IOK (VO < 0): –50 mA; (6)Continuous output current, IO: ±50 mA; (7)Continuous current through VCC or GND: ±100 mA; (8)Package thermal impedance, qJA: D package: 127℃/W, DB package: 158℃/W, PW package: 170℃/W; (9)Storage temperature range, Tstg: –65℃ to 150℃.

Features

SN74LVC08DR features: (1)EPIC (Enhanced-Performance Implanted CMOS) Submicron Process; (2)ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0); (3)Latch-Up Performance Exceeds 250 mA Per JESD 17; (4)Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25℃; (5)Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25℃; (6)Inputs Accept Voltages to 5.5 V; (7)Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK) and Flat (W) Packages, and DIPs (J).