Product Summary

The CS5824N receives four sets of 7-bit data in CMOS logic level and converts them into four lowvoltage differential signaling (LVDS)serial channels. The 7-bit input data is referenced to the CKIN signal. The RF pin selects either rising or falling edge trigger of CKIN. Parallel to serial conversion is performed by a 7X internal generated clock reference using onchip PLL using CKIN. A copy of CKIN but phaselocked to the output serial streams, CLKOUT, is also converted to the fifth LVDS channel. The CS5824N offers a reliable communication media using LVDS signaling and provides low EMI dealing with wide, high-speed TTL interfaces.

Parametrics

CS5824N absolute maximum ratings: (1)Supply voltage: 3 to 3.6 V; (2)VIH High-level input voltage: 2 V; (3)VIL Low-level input voltage: 0.8 V; (4)ZL Differential load impedance: 90 to 132 Ω; (5)TA Operating free-air temperature: 0 to 70 ℃.

Features

CS5824N features: (1)Four 7-bit serial and one clock LVDS channels; (2)Compatible with ANSI TIA/EIA-644 LVDS standard; (3)Wide CKIN ranges from 31MHz to 68MHz; (4)Fully integrated on-chip PLL that provides 7X CKIN serial shift clock; (5)Pin selectable for rising or falling edge trigger; (6)Support power-down mode; (7)5V/3.3V tolerant data input; (8)Single 3.3V supply operation; (9)CMOS low power consumption; (10)Functional compatible with DS90C385; (11)Available in 56-pin TSSOP package.

Diagrams

CS5824N BLOCK DIAGRAM