Product Summary

The DM9161EP is a physical layer, single-chip, and low power transceiver for 100BASE-TX 100BASE-FX and 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the Media Independent Interface (MII), the DM9161EP connects to the Medium Access Control (MAC) layer, ensuring a high inter-operability from different vendors. The DM9161EP uses a low power and high performance CMOS process. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE802.3u, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU). The DM9161EP provides a strong support for the auto-negotiation function, utilizing automatic media speed and protocol selection. Furthermore, due to the built-in wave-shaping filter, the DM9161EP needs no external filter to transport signals to the media in 100MBASE-TX or 10MBASE-T Ethernet operation.

Parametrics

DM9161EP absolute maximum ratings: (1)Supply Voltage:-0.3V to 3.6V ; (2)DC Input Voltage (VIN):-0.5V to 5.5V ; (3)DC Output Voltage(VOUT):-0.3V to 3.6V ; (4)Storage Temperature Rang (Tstg):-65℃ to +150℃; (5)Case Temperature:0℃ to 85℃; (6)Lead Temp. (TL, Soldering, 10 sec.):260℃.

Features

DM9161EP features: (1)Fully complies with IEEE 802.3u 10Base-T/100Base-TX/FX; (2)Support Auto-Negotiation function, compliant with IEEE 802.3u; (3)Fully integrated Physical layer single chip with direct interface to magnetic; (4)Integrated 10Base-T and 100Base-TX transceiver; (5)Selectable repeater or node mode; (6)Far end fault signaling option in FX mode; (7)Selectable MII or RMII (Reduced MII) interface, at he 100BASE-TX; (8)Selectable GPSI (7-Wired) or MII mode at the 10Base-T.; (9)Selectable twisted-pair or fiber mode output; (10)Selectable full-duplex or half-duplex operation; (11)MII management interface with maskable interrupt output capability; (12)Provide Loopback mode for easy system diagnostics; (13)LED status outputs indicate Link/ Activity, Speed10/100 and; (14)Full-duplex/Collision.; (15)Single low power Supply of 3.3V with 0.35μm CMOS technology; (16)Very Low Power consumption modes; (17)Compatible with 3.3V and 5.0V tolerant I/Os; (18)48-pin LQFP small package (1x1 cm).

Diagrams

DM9161EP Block Diagram

DM9102A
DM9102A

Other


Data Sheet

Negotiable 
DM9102D
DM9102D

Other


Data Sheet

Negotiable 
DM9161
DM9161

Other


Data Sheet

Negotiable 
DM9161A
DM9161A

Other


Data Sheet

Negotiable